1. Technical Field of the Invention
The present invention relates to controlling current levels in differential logic circuits, such as emitter-coupled logic (ECL) circuits and source-coupled logic (SCL) circuits, and particularly to setting the current levels in differential logic circuits without changing the output voltage swing thereof.
2. Background of the Invention
Emitter coupled logic (ECL) circuits are among the fastest types of integrated circuits. To obtain a high operating speed, ECL circuits are designed so that the bipolar transistors therein never saturate. The signals processed by ECL circuits are mostly differential signals, and each component of the differential signal is applied to a separate input of the differential circuit.
FIG. 1 represents a conventional ECL inverter circuit. The collector terminals of bipolar transistors Ta and Tb are connected to a positive supply Vdd through respective load resistors R and a bias current source I is connected between the emitter terminals of bipolar transistors Ta and Tb and negative supply Vss. The base terminals of transistors Ta and Tb receive the differential input signal Axe2x80x94A*. The differential output V is taken as a voltage between the collector terminals of transistors Ta and Tb.
ECL signals have a small voltage swing. In other words, the voltage difference between the high state and the low state of a component of an ECL signal is relatively small. This small voltage swing, which is approximately 0.5 volt, improves the speed of the ECL circuit by reducing and/or eliminating the time otherwise spent charging and discharging capacitances commonly found in ECL circuits.
The speed of the ECL and other differential logic circuits is mainly limited by the capacitances of the bipolar transistors therein. The collector terminal of a bipolar transistor has a time response inversely proportional to the collector current. Therefore, to increase the speed, high currents are typically used. The load resistors in an ECL circuit accordingly possess a relatively low resistive value in order to limit the voltage swing of the ECL signals to the desired value and to present a lower RC time constant relating to the transition time for an ECL signal. Because current continuously flows through a branch of an ECL circuit, a drawback of ECL circuits is the relatively high power consumption thereof.
Some ECL circuits are designed to operate at various frequencies. For example, some Asynchronous Transmission Mode (ATM) circuits operate at speeds of 155 and 622 Megabits per second (an ITU-I-432 standard).
It can be seen that differential logic circuits designed to operate at the highest possible speed operate at relatively high current levels and thus dissipate a relatively high amount of power. However, such high current levels are unnecessary for lower frequency applications.
A conventional approach to limit power consumption at lower speed applications is to adjustably lower the current levels in each ECL circuit. To maintain the same voltage swing, the load resistors in the ECL circuit are replaced with diodes. Thus, a steady voltage swing of approximately 0.7 volt is maintained for a variety of current levels. However, the resulting voltage swing is not compatible with standard ECL technology and varies with temperature. In addition, the presence of diodes increases the capacitances in the ECL circuit.
PCT application WO-A-93/18587 describes an ECL circuit whose power consumption is adjustable as a function of the operating frequency. The power consumption adjustment is effectuated by adjusting the bias current and the resistance of the load devices of the ECL circuit based upon the operating frequency. However, the circuitry for performing the current and resistance adjustments is relatively complex. For example, an adjustment signal would be a digital signal provided by a microprocessor. This digital signal would need to be converted to analog form before it can act on the bias current or on the load devices.
Another approach is described in U.S. Pat. No. 5,734,272 (the ""272 Patent), which shows an ECL circuit (FIG. 2) and corresponding control circuit therefor that modifies the current level in the ECL circuit as well as the resistances of the load transistors therein. It is noted, however, that load transistors Rv operate in the linear region of operation while bias transistor Rc (the transistor whose operating characteristics load transistors Rv are to match) operates in the saturated region of operation. The current transfer ratio of the current mirror including transistors Rc and Rv is thus not 1:1. Consequently, in order to maintain a constant voltage swing across load transistors Rv as the current Iv in the differential logic circuit is changed, a separate current source (Ic) must be used to bias load transistors Rv from the current source (Iv) used to bias input transistors Ta and Tb. The resulting current relationship for the differential logic circuit (equation 3; column 4, line 1 of the ""272 patent) also shows that the current relationship between currents Ic and Iv (and hence the control of the output voltage swing of the differential logic circuit) is dependent upon transistor dimensions, process parameters and temperature.
Based upon the foregoing, there is a need for the operating characteristics of the load transistors in a differential logic circuit and the bias current therein to substantially closely and easily follow each other, substantially without dependencies upon process parameters, device dimensions and temperature.
The present invention overcomes the shortcomings in prior differential logic circuits and control circuits therefor, and satisfies a significant need for a logic circuit having selected current levels while maintaining an output voltage swing that remains within a predetermine voltage range. In accordance with an embodiment of the present invention, there is provided a control circuit for a differential logic circuit including a current source and a pair of load transistors. The control circuit includes a pull-down transistor having a first conduction terminal coupled to a first voltage source, a second conduction terminal and a control terminal coupled to the current source of the differential logic circuit so as to form a current mirror therewith; a pull-up transistor having a control terminal coupled to the control terminal of the load transistors, a first conduction terminal coupled to a second voltage source and a second conduction terminal; and a controlled current source coupled between the pull-up transistor and the pull-down transistor. The controlled current source receives an input signal that controls the level of current passing through the differential logic circuit and the resistance of the load transistors, wherein the product of the current passing through the load transistors and the resistance thereof does not substantially vary.
The operation of the control circuit and corresponding differential logic circuit includes selecting a current level passing through the controlled current source, which sets the current level of the current source in the differential logic circuit to the desired level. The selected current level also sets the operating characteristics of the pull-up transistor, which thereupon sets the operating characteristics of the load transistors of the differential logic circuit. The current level of the differential logic circuit and the resistance level of the load transistors are inversely proportional to each other. In this way, a single selected current level of the control circuit sets the current level and thus the speed of the differential logic circuit while maintaining an output voltage swing thereof that does not substantially vary.